In deep submicron digital circuit structures, transistors sizes have been scale down and supply voltages and switching thresholds have been reduced to create faster circuits. As a result, transistor switches cannot be completely switched off. This causes leakage current to flow from source to drain, which results in a problematic loss of power in combinational cells and sequential cells.
To address this problem, fabricators of silicon structures of ninety nanometers and smaller have created logic library variants with different transistor switching thresholds that can be mixed together. To some degree this allows for power optimization by swapping between different threshold classes for each logic cell depending on the timing budget. However, this has not been a satisfactory solution.
What is needed, therefore, are submicron digital switching circuits having low switching thresholds and low leakage currents.